1. Field of the Invention
The present invention generally relates to a method of manufacturing a T-gate field effect transistor (FET) and, more particularly, to a method of manufacturing a viable T-gate FET even when the cap of the "T" is mis-aligned from the stem of the "T".
2. Description of the Related Art
In conventional FET processing the limits of the poly gate length and the channel length are dependent on the lithography resolution. The self-aligned, or symmetrical, T-gate transistor allows for a lithography-independent sub 0.1 .mu.m channel and a longer gate while optimizing resistance and capacitance characteristics.
Self-aligned FETs are widely used in high speed integrated circuits to minimize the gate-source and gate-drain parasitic capacitance. Most self-aligning processes use a refractory metal as a mask for self aligning implantation of the n+ (or p+) source and drain regions. In these processes, it is important to control the distance between the gate conductor and the n+ source and drain implant regions since these parameters effect the speed and performance of the FET.
Control of n+ source and drain implants to the gate metal may be accomplished by using a T-shaped gate. Conventionally, this requires the deposition of another layer, either a dielectric or metal, on top of a refractory metal and acts as the mask for subsequent etching and undercutting of the underlying refractory gate. The etching process is done either by wet chemical etch or dry etching. The sacrificial top layer is then removed prior to high temperature annealing of the n+ source and drain implants due to lack of high temperature stability of the top layer. Removing the top layer eliminates the choice of fabricating the ohmic metal contacts in a self-aligned manner with respect to the gate metal.
U.S. Pat. No. 5,550,065 to Hashemi et al. discloses a method for fabricating a self-aligned FET on a surface of a semiconductor substrate using LaB /TiWN as a T-shape gate structure formed by a controllable dry etching of the TiWN using LaB.sub.6 as the mask which allows control of n+ implant distance to gate edge. The high temperature stability of the LaB.sub.6 /TiWN structure allows the "T-shaped" gate to be preserved during the high temperature post n+ source and drain implant annealing step and subsequently to be used for the self-aligned formation of source and drain ohmic contact metals on the surface of the substrate and in spaced relationship while simultaneously depositing extra low resistance metal over the "T-shaped" gate metal, producing low gate resistance.
The process for manufacturing T-shaped gates requires high tolerances between the cap (horizontal top) of the "T" and the stem (the vertical portion) of the "T". When forming the cap of the T with a subtractive etch process, if there is any mis-alignment between the cap and the stem, some of the stem of the T will be accidentally but unavoidably etched away leading to device failure.
U.S. Pat. No. 4,965,218 to Geissberger et al. discloses a self aligned T-gate FET which allows for misalignment between the cap of the T and the stem of the T while still producing a viable device. In particular, windows are patterned in an encapsulant layer over the gate area. A non-critically aligned photoresist mask over the encapsulant layer is used to expose substantially the entire top surface of the stem of the T-gate. Gold is subsequently evaporated onto the photoresist and gate stem and lifted off with the photoresist to produce a non-critically aligned (+/-0.5 micron) cap of the T-gate which is firmly bonded to the stem. The technique allows for gross misalignment between the cap and the stem of the T-gate metallization without increasing the FET gate length. Hence, the stem and the cap can be substantially mis-aligned with respect to one another and still produce a viable operating device. However, this method relies on an encapsulant layer to protect the stem portion of the T-gate as the cap is formed and further is expensive owing to the use of gold as the material for the cap.